Job Details

Role Number: 200624413-3760

Summary

Apple is building the world’s fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency, and high-bandwidth. In this role, you will work on crafting special purpose cache and controller which is part and parcel of the SOC memory hierarchy.

Minimum Qualifications

• 10 + years of full time ASIC design experience

• memory system development

• RTL/micro-architecture definition

• PPA (performance/power/area) analysis

• Cache design background including an understanding of different memory organizations and tradeoffs.

• Hands on Experience with multi-processor cache coherence protocols

• B.S. in a relevant field

Preferred Qualifications

• Knowledge of high-performance coherent memory systems or interconnect architectures

• Knowledge of high-performance DRAM controller

• M.S in a relevant field.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (https://www.eeoc.gov/sites/default/files/2023-06/22-088_EEOC_KnowYourRights6.12ScreenRdr.pdf) .