Job Details

Role Number: 200647828-0836

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Responsible for timing to ensure that chips deliver expected performance. Use Static Timing Analysis tools such as Prime Time Analyze for timing with multiple clock and power domains. Apply knowledge of timing corners, process variations, signal integrity issues and operating conditions. Understand Noise Analysis to help fix it in the design. Use Tcl, Perl, and Python tools to automate tasks. Use SDC commands like clock definitions, timing exceptions, IO constraints. Understand clock domain crossings. Debug capacitance issues and transition violations seen in the run. Work on signoff checks to enable chips to take out. Collaborate with logic design, physical design teams using Verilog and layout. Support the team with design rule checks. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $156,853 - $220,900/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

• Master’s Degree or foreign equivalent in Electrical and Computer Engineering, Integrated Circuits or related field and 1 year of experience in the job offered or related occupation.

• 1 year of experience with each of the following skills is required:

• Utilizing Static timing analysis concepts, including setup, hold timing checks to close timing on designs

• Leverage knowledge of working with place and route tools to provide feedback on implementation issues

• Using STA tools to launch and facilitate full chip integration runs for timing verification

• Using design architecture and SDC constraints knowledge to provide feedback to design teams

• Comparing run results by reviewing the timing reports

• Applying concepts of device physics to address power and performance concerns

• Using liberty files to understand timing requirements such as setup, hold and max transition requirements

• Using Scripting tools including Perl and Python to automate tasks

Preferred Qualifications

• N/A

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (https://www.eeoc.gov/sites/default/files/2023-06/22-088_EEOC_KnowYourRights6.12ScreenRdr.pdf) .