Job Details

Role Number: 200659753-0836

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Deliver Analog Mixed-Signal IP in a SOC flow. Craft sophisticated layouts for mixed-signal and analog circuits, review floor plans, and analyze intricate circuits with circuit designers. Run complete sets of design verification tools, plan/schedule work, and coordinate vital layout tradeoffs. Interpret LVS (Layout Vs. Schematic), DRC (Design Rule Check), ERC (Electrical Rule Check), EMIR (Electro-migration and Current/Resistance Drop), and PDV (Physical Design Verification) reports to find the fastest way to complete the layout, exceeding engineering specifications and expectations. Delegate and coordinate tasks to a group of contractors and check the layout quality and its on-time delivery. Participate in layout methodology and CAD initiatives to create innovative ways to boost layout efficiency and productivity. Take part in evaluating the next breakthrough of new advanced technology nodes. Collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCS. Craft sophisticated layouts for mixed-signal and analog circuits, review floor plans, and analyze intricate circuits with circuit designers. Run complete sets of design verification tools, plan/schedule work, and coordinate vital layout tradeoffs. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $168,583 - $213,700/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

• Bachelor’s degree or foreign equivalent in Electronic Engineering, Electronics and Communications, or a related field and 4 years of experience in the job offered or related occupation.

• 4 years of experience with each of the following skills is required:

• Using tools to navigate and create project related technology config, workspace, LEF (Library Exchange Format). Performing snap design (release tool) on schematic and layout megacells.

• Actively participating in automation development activities. Writing spec for CAD to execute.

• Efficiently navigating, debugging and fixing EMIR (Electro-migration and Current/Resistance Drop) violations.

• Providing feedback to ESD (Electrostatic Discharge) and tech teams for enhancement requests. Conducting meaningful layout reviews. Setting priorities for block or megacells to meet quality and deadline for each milestones.

• Creating and analyzing RC (resistance & capacitance) extraction to debug and fix layout mismatches. Using and teaching Paragon X tool to others.

• Providing circuit designers with ways to improve schematics for layout implementation.

• Providing circuit designers with recommendations on technology impact (know what design rule checks (DRC) are possible or not.

• Debugging and fixing complex design rule check (DRC) and layout Vs. schematic (LVS) violations: Latch-up, ESD (Electrostatic Discharge), transistor hookup errors & short circuits.

• Creating various groups, width/Space patterns (WSP), toolbar, layout editor, layer manipulation, check in & check out data, XL (Cadence Extended Layout Suite) compliant.

Preferred Qualifications

• N/A