Job Details

Physical Design Engineer

Cupertino, California, United States

Hardware

Summary

Posted: May 22, 2025

Weekly Hours: 40

Role Number: 200605074

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Work with the FE team to understand chip architecture and drive physical aspects early in the design Cycle. Work with the physical design team, drive methodologies and "best-known methods" to streamline
physical design work, develop guidelines and checklists, drive execution, and track progress. Serve as a focal point for place and route, drive the work among place and route engineers, set goals and milestones, plan short and long-term work, and understand dependencies between different domains like top, STA, block place, and route. Resolve design and flow issues related to the physical design, identify potential I solutions, and drive execution. Perform partitioning on the full chip or chiplets to split the design and plan feedthrough connectivity through them. Plan physical pin placement for the interfaces for direct and feedthrough connections. Plan and implement reference and PLL output clocks using custom techniques and clock tree synthesis. Perform custom Power implementation to meet IP integration specifications and power domain transition region requirements. Verify and Fix design rule checks for manufacturability and circuit connections shorts and opens. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $163,872 - $214,500/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

• Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering or related field and 2 years of experience in the job offered or related occupation.

• 2 years of experience in each of the following skills is required:

• 1. Using EDI or ICC tools to build a physical design database for the system on Chip
• 1. Utilizing STARRC and primetime for static timing analysis on these designs
• 1. Using conformal or VCLP to verify power domain crossing issues in the physical designs and RTL vs netlist integrity.
• 1. Using Calibre or PVS tools for Design rule verification for manufacturability and Layout verification for checking the circuit sanity.
• 1. Using RedHawk or Voltus to check the Dynamic and static IR drop issues in the design.
• 1. Experience in Floorplan, IO placement, and Macro placement to achieve high-density layout design.
• 1. Experience in die size estimation based on technology node scaling and layout density achievable for each node.
• 1. Experience in Clock Tree synthesis using EDA tools and custom implementation for high-frequency interfaces.

Preferred Qualifications

• N/A

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant (https://www.eeoc.gov/sites/default/files/2023-06/22-088_EEOC_KnowYourRights6.12ScreenRdr.pdf) .

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant (https://www.eeoc.gov/sites/default/files/2023-06/22-088_EEOC_KnowYourRights6.12ScreenRdr.pdf) .

Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation.

Apple participates in the E-Verify program in certain locations as required by law.Learn more about the E-Verify program (https://www.apple.com/jobs/pdf/EverifyPosterEnglish.pdf) .

Apple is committed to working with and providing reasonable accommodation to applicants with physical and mental disabilities. Reasonable Accommodation and Drug Free Workplace policy Learn more .

Apple is a drug-free workplace. Reasonable Accommodation and Drug Free Workplace policy Learn more .

Apple will consider for employment all qualified applicants with criminal histories in a manner consistent with applicable law. If you’re applying for a position in San Francisco, review the San Francisco Fair Chance Ordinance guidelines applicable in your area.

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