Job Details

Role Number: 200652092-0836

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Drive the netlist-to-layout convergence flow, carry out Physical Design of Apple's latest CPU products. Optimize power, performance and area of design through synthesis, and place and route tools. Experiment on CPU microarchitecture, and make tradeoffs between power, performance and area. Verify the correctness of the design. Use simulation and other verification techniques to validate the functional, timing and electrical requirements of the CPU blocks. Debug the physical design flow based on verification results. Work closely with cross-functional teams, including top-level integration teams, to discuss and solve issues related to CPU floorplanning, timing, power distribution, reliability, and testability. Collaborate with the logic design team to understand partition architecture and drive physical aspects early in the design cycle. Resolve design and flow issues related to physical design, identify potential solutions, and drive execution. Develop and automate scripts to enhance productivity and ensure consistency across physical design projects. Participate in establishing CAD and physical design methodologies for correct and design constructions with better quality. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $146,711 - $190,900/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

• Master's degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or a related field.

• Experience and/or education must include:

• Using logic synthesis tools, including Cadence Genus, to compile and design netlist and provide quality feedback to logic design team.

• Creating and refining netlist-to-layout convergence processes, leveraging Place and Route EDA tools including Cadence Innovus.

• Writing Python scripts to enhance productivity, focusing on efficiency and repeatability in physical design tasks.

• Writing TCL scripts to interface with EDA tools for tasks like floorplanning, clock tree synthesis, and timing optimization.

• Writing Perl scripts extend the functionality of existing scripts and ensure compatibility with modern design workflows and processes.

• Leveraging Synopsys PrimeTime and Cadence Tempus to analyze timing violations and implement fixes, ensuring designs meet critical timing constraints.

• Managing design iterations using systems Perforce to maintain source integrity and enable collaboration across global teams.

• Leveraging data visualization tools including Python matplotlib to provide general analysis of design quality.

• Using Jira and Radar to track project timelines, cross-functional collaboration and tasks assignments.

• Utilizing Synopsys IC Validator to conduct design rule checks (DRC) and layout versus schematic (LVS) verification, ensuring design adherence to foundry guidelines and resolving violations efficiently.

Preferred Qualifications

• N/A

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (https://www.eeoc.gov/sites/default/files/2023-06/22-088_EEOC_KnowYourRights6.12ScreenRdr.pdf) .