Job Details

Physical Design Engineer

Austin, Texas, United States

Hardware

Summary

Posted: May 08, 2025

Weekly Hours: 40

Role Number: 200602715

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Austin, Texas. Work with front end (FE) team to understand chip architecture and drive physical verification aspects early in design cycle. Working on full chip design rule checking (DRC), layout vs schematic design rule checking (LVS DRC) and physical design verification (PDV) analysis flows. Work with physical design team, drive methodologies and “best known methods” to streamline physical design work come up with guidelines and checklists, drive execution, and track progress while offering physical verification support. Support part it ion owners with PnR activities, set goals, plan short and long-term work, understand dependencies between different domains like top, static timing analysis (STA), block place and route (PNR). Resolve design and flow issues related to physical design, identify potential solutions and drive execution. 40 hours/week.

Minimum Qualifications

• Master's degree or foreign equivalent in Electrical Engineering or related field and one year of experience in the job offered or related occupation

• Education and/or experience with the following skills is required:

• Experience with design rule checking (DRC) and implementation methodologies at both partition and top design levels.

• Experience with layout versus schematic (LVS) verification

• Leveraging Antenna (ANT) analysis to identify and mitigate potential reliability issues in integrated circuits

• Guide partition floorplanning by incorporating recommended foundry requirements and group place and route (PNR) specifications.

• Use Python, TCL, or Perl to debug and handle documentation.

• Experience with the top and partition place and route (PNR) design process.

• Experience with industry standard PNR tools such as Cadence, Synopsys, or Mentor Graphics.

• Digital design fundamentals including understanding of digital logic design principles.

• Knowledge of digital circuits and their functionality.

• Working knowledge of related design principals in static timing analysis (STA), electrical analysis (EA), formal equivalence (LEQ), and low power design.

Preferred Qualifications

• N/A

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant (https://www.eeoc.gov/sites/default/files/2023-06/22-088_EEOC_KnowYourRights6.12ScreenRdr.pdf) .

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant (https://www.eeoc.gov/sites/default/files/2023-06/22-088_EEOC_KnowYourRights6.12ScreenRdr.pdf) .

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